This invention relates to programmable logic array integrated circuits, and more particularly to improved organizations of the logic regions and interconnection conductors of such devices.
Several different xe2x80x9carchitecturesxe2x80x9d for programmable logic array devices are known. Pedersen et al. U.S. Pat. No. 5,260,610, for example, shows programmable logic array devices in which blocks of programmable logic regions are disposed on the device in a two-dimensional array of intersecting rows and columns of such blocks. Each block includes a plurality of logic regions and a plurality of local feedback conductors for making the output of any logic region in the block selectively available as an input to any logic region in that block. Global horizontal conductors are associated with each row of blocks for conveying signals between the blocks in that row. Global vertical conductors are associated with each column of blocks for conveying signals from row to row.
The Pedersen et al. architecture has many advantages such as relatively high-speed signal conduction due to the continuous, long, global horizontal and vertical conductors. In some applications, however, this architecture may have certain disadvantages. For example, the blocks are relatively large (e.g., 16 logic regions each), so that relatively large numbers of programmable switches or connectors are required in the local feedback circuitry in each block to make the output of each region available as a possible input to any logic region in the block.
Another possible disadvantage is that any interconnection between blocks uses up at least one global conductor, even though the interconnection may be relatively short (e.g., just to an adjacent block). Also, because the logic region inputs are fed directly from the global horizontal conductors, each global horizontal conductor has many programmably switchable taps along its length. These taps cause significant loading of the global horizontal conductor circuits, which tends to increase the power required to drive those circuits, and which also tends to make those circuits not as fast as they would be with fewer programmable taps.
An architecture which addresses some of the possible disadvantages of the Pedersen et al. architecture is shown in Cliff et al. U.S. Pat. No. 5,260,611. The Cliff et al. architecture reduces the number of switchable taps on the global horizontal conductors by tapping those conductors to block input conductors associated with each block, the number of taps and the number of block input conductors associated with each block being less than the total number of inputs to the logic regions in the block. Each block input conductor is programmably selectively connectable to any logic region in the block, although the number of logic regions in each block is reduced from 16 to eight as compared to the Pedersen et al. architecture.
While the Cliff et al. architecture offers some possible improvements over the Pedersen et al. architecture, it does not improve on the Pedersen et al. architecture in other respects. The Cliff et al. architecture still requires an entire global horizontal or vertical conductor to be used for even relatively short interconnections between blocks. And the Cliff et al. architecture still requires that relatively large programmable connector matrices be provided in each block to make the output of each logic region in the block, as well as each block input conductor, available as an input to any logic region in the block. For example, to make any of eight logic region output signals and any of 24 block input conductors available as inputs to any of the four inputs of each of eight logic regions, a matrix of (8+24)xc3x974xc3x978=1024 programmable connectors is required for each block. In addition to these programmable connectors, other programmable connectors are required to connect the block input conductors to the global horizontal conductors, to apply the logic region outputs to the global horizontal and global vertical conductors, and to interconnect the global horizontal and global vertical conductors. None of these programmable connectors is typically performing any logic, and in all cases many of these connectors are unused.
A very different type of architecture is shown in Freeman U.S. Pat. No. Re. 34,363. In this architecture short interconnection conductors adjacent to each logic region are programmably interconnectable to one another to make interconnections between any but the most closely adjacent logic regions. A possible disadvantage of this architecture is that large numbers of short conductor segments must be xe2x80x9cpieced togetherxe2x80x9d to make long interconnections, which tend to be relatively slow due to the large number of programmable switches that the interconnection signal must pass through. More recent commercial products of Freeman""s assignee, Xilinx, Inc., have added longer, uninterrupted conductors, and also uninterrupted conductors between adjacent logic regions (see, for example, Carter U.S. Pat. No. 4,642,487). However, these products still rely heavily on piecing together many relatively short interconnection conductor segments to make certain kinds of interconnections.
Another architecture which relies on programmably piecing together axially aligned and adjacent conductors to make longer conductors is shown in El Gamal et al., xe2x80x9cAn Architecture for Electrically Configurable Gate Arrays,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, April 1989, pp. 394-98; El-Ayat et al., xe2x80x9cA CMOS Electrically Configurable Gate Array,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 24, No. 3, June 1989, pp. 752-62; and Elgamal et al. U.S. Pat. No. 4,758,745). This architecture is not reprogrammable. Thus it uses one-time-only programmable connection elements that tend to be smaller and have less circuit loading and signal delay than typical reprogrammable connection elements. With such small one-time-only programmable elements it may be acceptable to provide excess interconnection capacity (e.g., regions of interconnection which are very densely or even fully populated with programmable connection elements) and to rely extensively on piecing together multiple short conductors to make longer conductors. But when a device is to be made reprogrammable, the larger size, loading, and delay of reprogrammable connection elements puts much greater pressure on the device designer to economize as much as possible on the use of such elements, without, of course, unduly sacrificing flexibility in the use of the resulting device. Similar economies are also of interest in connection with one-time-only programmable devices, especially as the logic capacity of those devices increases.
In view of the foregoing, it is an object of this invention to provide improved organizations for the logic regions and interconnection conductors of programmable logic array integrated circuit devices.
It is another object of this invention to provide programmable logic array integrated circuit devices having more effective signal routing, high speed, and greater logic capacity per unit of silicon area.
It is still another object of this invention to reduce the number of programmable switches or connectors that must be provided in programmable logic array devices, to reduce the number of global conductors that must be provided in such devices, and to avoid the piecing together of large numbers of short interconnections conductors that is characteristic of some prior devices.
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic array integrated circuit devices in which the blocks of logic regions are grouped together in super-blocks of several (e.g., four) blocks each. The super-blocks are typically disposed on the integrated circuit in a two-dimensional array of intersecting rows and columns. Global horizontal conductors are associated with each row of super-blocks for making interconnections between super-blocks in the associated row. Global vertical conductors are associated with each column of super-blocks for making interconnections between the rows.
Each block has local feedback conductors for making the outputs of the logic regions in that block available to the inputs of the logic regions in the block. The outputs of the logic regions in each super-block are also applied to inter-block conductors associated with that super-block in order to facilitate application of the outputs of the logic regions of each block to the logic regions of other blocks in the same super-block.
Super-block feeding conductors associated with each super-block allow signals on the associated global horizontal conductors to enter the super-block. These super-block feeding conductors can also receive the signals on the inter-block conductors associated with the super-block. Programmable switch or logic connector matrices are associated with each super-block for selectively connecting the inputs of each logic region in the super-block to the associated super-block feeding conductors and also to the local feedback conductors of the block which includes that logic region. The inter-block conductors are additionally used to convey signals out of each super-block to the global horizontal and vertical conductors.
Because of the availability of alternate local feedback routes through the inter-block and super-block feeding conductors, the programmable logic connector matrices connecting the logic region inputs to the associated local feedback conductors can be less than fully populated. This saves a considerable number of programmable logic connectors. The provision of the inter-block conductors greatly reduces the need for global conductors to make connections between blocks. The use of one set of super-block feeding conductors to feed several blocks (e.g., the four blocks in a super-block) makes more efficient use of this type of resource.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.